PORTFOLIO:

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Circuit 6: Pattern Matcher (Simon Says) — EPROM-driven breadboard

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Inputs, outputs, and behavior

Inputs

• BTN[3:0] — 4-bit keypad output through a 7414 Schmitt inverter chain. The four playable values map to keypad codes 0, 1, 4, and 5.
• Data — the keypad encoder’s data-available pin. High while a key is held. The PM-FSM uses this as the “press is active” signal; no four-input OR across the BTN lines required.
• EPROM_OUT[3:0] — data lines D[3:0] from the 27C64. D[7:4] are unused. The byte at the current pm_counter address holds the 4-bit code for the value expected at that step.
• LDPM (RESET) — pushbutton: asynchronously loads pm_counter to 1 and clears the PM-FSM state register to LISN. Used to start a new run.
• CLK — LM555 free-running clock, ~1.5 Hz at the demo configuration. Drives the PM-FSM state register and the MATCH latch.

Outputs

• INC_PM — Mealy pulse on CHEK → LISN release with MATCH = 1. Increments pm_counter to the next address.
• LOSE_FLAG — Mealy pulse on CHEK → LISN release with MATCH = 0. Drives the LOSE LED.
• step_counter[3:0] — the 4-bit counter, also driving EPROM ADDR[3:0]. Surfaced on four LEDs so the current step is visible.
• MATCH — latched comparator value, on an LED so the player can see “the press was registered as correct” while the button is held, before the release event fires.

Behavior

• Start a run: press RESET. pm_counter loads to 1, PM-FSM state clears to LISN.
• Correct press: on the press touch, the PM-FSM transitions LISN → CHEK and the MATCH latch captures the comparator’s “match” value (high). The MATCH LED lights. On release, the FSM transitions CHEK → LISN and INC_PM pulses, advancing pm_counter to the next address.
• Wrong press: the MATCH latch captures “no match” (low) on the press touch; MATCH LED stays dark through the hold. On release, the FSM transitions CHEK → LISN and LOSE_FLAG pulses, lighting the LOSE LED. pm_counter holds.
• Held button: the FSM holds in CHEK as long as a button is pressed, so a held button doesn’t repeat-fire its event. The event fires exactly once on the release edge.
• Reset: pressing RESET at any point reloads pm_counter to 1 and forces the FSM back to LISN.

Boolean expressions and tables

PM-FSM state encoding (single state bit):

| State | Bit | Meaning                                     |
|-------|-----|---------------------------------------------|
| LISN  |  0  | waiting for a press                         |
| CHEK  |  1  | press held, MATCH latched, ready to evaluate|

State transition table (Mealy pulses fire on the listed transition):

| From | Condition                  | To   | Mealy pulses |
|------|----------------------------|------|--------------|
| LISN | Data                | CHEK | MATCH_LD_EN  |
| LISN | else                       | LISN | —            |
| CHEK | Data' · MATCH       | LISN | INC_PM       |
| CHEK | Data' · MATCH'      | LISN | LOSE_FLAG    |
| CHEK | else (button held)         | CHEK | —            |

Final equations (state register is one JK flip-flop, encoded LISN = 0 and CHEK = 1):

Comparator (7485, 4-bit equality):
  COMP = (BTN[3:0] == EPROM_OUT[3:0])      (taken from the A=B output)

MATCH latch (JK-FF, clock-enabled on the LISN → CHEK transition):
  MATCH_LD_EN = LISN · Data
  J(MATCH)    = MATCH_LD_EN · COMP
  K(MATCH)    = MATCH_LD_EN · COMP'

PM-FSM next-state (JK-FF, J=K=0 holds):
  J(state) = Data
  K(state) = Data'

Mealy outputs (one-cycle pulses on the CHEK → LISN transition):
  INC_PM    = CHEK · Data' · MATCH
  LOSE_FLAG = CHEK · Data' · MATCH'

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Circuit 7: Game Controller FSM (Simon Says) — CircuitVerse simulation

Open the CircuitVerse simulation →

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Detailed reference manual

Full state encoding, event codes, output table, round counter and random start-address subsystem documentation, and the test-procedure walkthrough for the CircuitVerse simulation:

Inputs, outputs, and behavior

Inputs

• E0, E1, E2 — 3-bit event code from the priority-encoder front-end (MSB first). Five named events: START (000), PD_FIN (001), LOSE (010), ADV (100), WIN (101).
• CLK — clock. The event register latches on the rising edge; the state register samples on the falling edge (two-phase arrangement keeps multi-bit event transitions from reaching the FSM mid-update in the CircuitVerse simulation).
• RESET — asynchronous clear. Forces the state register to IDLE (00) and clears the WIN and LOSE latches and the round counter on the way down.

Outputs

Moore (state-only level signals):

• PLAYD — high in PLAY only. Drives the Pattern Display enable and the color LED bank.
• USERD — high in USER only. Drives the Pattern Matcher enable and the EPROM ADDR mux select.

Mealy (one-clock pulses on transitions):

• LDPD — parallel-load the Pattern Display step counter to the round’s start address. Fires on START·IDLE and ADV·USER.
• LDPM — parallel-load the Pattern Matcher’s user-turn counter at the start of the player’s turn. Fires on PD_FIN·PLAY.
• RINC — increment the round counter on a successful round. Fires on ADV·USER.
• SLOSE — set the LOSE latch on a wrong color or timeout. Fires on LOSE·USER.
• SWIN — set the WIN latch on the final-round completion. Fires on WIN·USER.
• GMRST — game reset. Clears the WIN and LOSE latches and the round counter at game start. Fires on START·IDLE.

Behavior

• IDLE → PLAY: START fires GMRST (clearing the end-game latches and the round counter) and LDPD (loading the Pattern Display from the random start address). The machine begins showing the sequence.
• PLAY → USER: PD_FIN fires once the Pattern Display has finished playing the round’s sequence. LDPM loads the Pattern Matcher’s user-turn counter; the player’s turn begins.
• USER → PLAY: ADV fires after a successful round with more rounds remaining. RINC increments the round counter and LDPD re-loads the Pattern Display for the next, longer sequence.
• USER → IDLE: either LOSE (wrong color or response-timer expiry) or WIN (final round complete) drops the FSM back to IDLE. SLOSE or SWIN sets the corresponding end-game latch.
• BLNK recovery: the unused 4th 2-bit code (Q0 Q1 = 10) is unreachable in normal clocked operation, but the manual Q1′ insurance term in K(Q0) guarantees that any glitch into BLNK returns to IDLE on the next clock edge regardless of event.

Boolean expressions and tables

State encoding (Q0 = MSB, Q1 = LSB):

| State | Q0 | Q1 | Meaning                                          |
|-------|----|----|--------------------------------------------------|
| IDLE  |  0 |  0 | between games — waits for START                  |
| PLAY  |  0 |  1 | Pattern Display playing the round’s sequence     |
| USER  |  1 |  1 | user pressing color buttons                      |
| BLNK  |  1 |  0 | unreachable in normal operation — recovery row   |

State transition table (Mealy pulses fire on the listed transition):

| From | Event   | To   | Mealy pulses     |
|------|---------|------|------------------|
| IDLE | START   | PLAY | LDPD, GMRST      |
| IDLE | else    | IDLE | —                |
| PLAY | PD_FIN  | USER | LDPM             |
| PLAY | else    | PLAY | —                |
| USER | ADV     | PLAY | LDPD, RINC       |
| USER | LOSE    | IDLE | SLOSE            |
| USER | WIN     | IDLE | SWIN             |
| USER | else    | USER | —                |
| BLNK | any     | IDLE | —                |

Final equations after the architecture sweep, Class A encoding, JK flip-flop pivot, BLNK don’t-care, and the manual Q1′ insurance term — 58 input cost / 18 gate cost from LogicAid Petrick:

Next-state logic:
  J(Q0) = PD_FIN · Q1
  K(Q0) = LOSE + ADV + WIN + Q1'           (Q1' = BLNK recovery insurance)
  J(Q1) = START
  K(Q1) = (LOSE + WIN) · Q0

Moore outputs:
  PLAYD = Q0' · Q1
  USERD = Q0                               (direct wire from the state bit)

Mealy outputs:
  GMRST = START · Q1'
  RINC  = ADV   · Q0
  SLOSE = LOSE  · Q0
  SWIN  = WIN   · Q0
  LDPM  = PD_FIN · PLAYD
  LDPD  = GMRST + RINC                     (shared subexpressions across LDPD’s two terms)

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Circuit 8: Volleyball Lineup Tracker — CircuitVerse simulation

Open the CircuitVerse simulation →

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Inputs, outputs, and behavior

Inputs

• DATA[3:0] — 4-bit shared parallel-load data bus. The new jersey number for a substitution (0–15).
• ADDR[2:0] — 3-bit court position select for substitution. Codes 001–110 are valid (positions P1–P6); 000 and 111 are unused.
• ROTATE — momentary button. Each click arms Counter A, which fires a 4-pulse clock burst to all six cells. Lineup advances one position around the ring.
• SUB — momentary button. Each click arms Counter A (reused) and the control FF, briefly enables the decoder, and emits clock pulses to all six cells in parallel; only the addressed cell’s gated CLK actually fires, so only that cell parallel-loads.
• CLK — free-running fast clock. Shared by the counter and the rest of the timing.

Outputs

• P1[3:0] through P6[3:0] — the 4-bit jersey number currently at each court position. Position numbering follows standard volleyball convention: P1 is the server (back-right), P2 front-right, P3 front-center, P4 front-left, P5 back-left, P6 back-center.
• Per-position display — each cell’s 4-bit output exposed on LEDs.

Behavior

• Rest state: neither button pressed; Counter A idle; control FF HIGH; decoder disabled (all DEC outputs HIGH); all six cells’ SRE inputs HIGH (shift mode default); no clock pulses fire to any cell. The lineup holds.
• ROTATE press: Counter A arms, four CLK pulses pass through to all six cells in parallel. All cells are in shift mode, so each clock shifts one bit through the chain. After four clocks the lineup has advanced one position; P6’s player has become the new P1.
• SUB press: the control FF drops LOW, asserting the decoder’s active-low enable. The decoder latches ADDR; the addressed line (DEC[addr]) goes LOW while the other five stay HIGH. That cell’s SRE drops to LOAD mode; the other five remain in shift mode. CLK pulses fire from Counter A out to all six cells in parallel, but a per-cell AND with each cell’s SRE gates them: only the addressed cell (SRE LOW) actually sees a rising edge. That cell parallel-loads from DATA; the other five hold. At the end of Counter A’s window the control FF resets HIGH, the decoder turns off, all SREs return HIGH, the lineup is in shift-mode default again.

Boolean expressions and tables

Serial-chain wiring. Each cell’s SRL (incoming serial bit) is fed by the previous-lower-indexed cell’s SRQ (outgoing serial bit), with cell[0]’s SRL wrapping to cell[5]’s SRQ to close the ring:

cell[0].SRL = cell[5].SRQ      (P1 ← P6; wraparound — P6’s player becomes the new server)
cell[1].SRL = cell[0].SRQ      (P2 ← P1; old server advances to front-right)
cell[2].SRL = cell[1].SRQ      (P3 ← P2)
cell[3].SRL = cell[2].SRQ      (P4 ← P3)
cell[4].SRL = cell[3].SRQ      (P5 ← P4)
cell[5].SRL = cell[4].SRQ      (P6 ← P5)

Generalized: cell[i].SRL = cell[(i−1) mod 6].SRQ (cell[0] wraps to cell[5]). Over four CLK pulses the full 4-bit jersey number transfers from cell i−1 into cell i.

Per-cell clock and mode-select wiring:

cell[i].CLK = SRPR_CLK_SHIFT + (SRPR_CLK_LOAD · SRE[i]')     (OR of the two clock paths; LOAD path is per-cell AND-gated)
cell[i].SRE = DEC[i]                                       (direct wire from the decoder — polarities match)

Decoder behavior. Active-low enable driven by the control flip-flop; default-HIGH outputs when disabled, addressed line LOW when enabled:

DEC_ENABLE_n = control_FF_Q          (HIGH at rest = decoder off)

DEC[k] = 1 (HIGH) for all k          when DEC_ENABLE_n = HIGH    (default, decoder off)
DEC[k] = NOT(ADDR == k)              when DEC_ENABLE_n = LOW     (addressed line LOW, others HIGH)

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Circuit 3: MUX-based 4-bit 2’s complement adder with signed, base-10 display (breadboard)

Inputs / outputs / behavior

Inputs

• X: 4-bit 2’s complement on DIP switches (range −8 to +7)
• Y: 4-bit 2’s complement on DIP switches (range −8 to +7)

Outputs

• Two seven-segment displays showing the magnitude of the signed result (0 to 16)
• Sign LED — lit when the result is negative

Behavior

Each 4-bit input is sign-extended to 5 bits and added by two 74283 chips: one sums bits 0–3, and one stage of the second chip computes bit 4 from the replicated MSBs. The 5-bit signed result has range −16 to +14. The MSB drives the sign LED and serves as the select for a 74157 quad 2-to-1 MUX, which routes either the positive-side or negative-side BCD path through to the 7447 decoders. On the positive side, the magnitude bits feed the BCD functions directly. On the negative side, the raw adder bits encode 16 minus the magnitude (a property of 2’s complement arithmetic), and the BCD functions are derived to read that representation correctly. Either path produces the same BCD output the displays need.

Boolean expressions and truth tables

Variables

Following the numbering convention used throughout the design: a is the sign bit, and b through e are the magnitude bits from MSB to LSB. BCD outputs are T (tens, single bit since the result range caps at magnitude 16) and N0–N3 (ones BCD, 8-weight through 1-weight). N3 is e directly — no MUX needed.

Tens digit T

T equals 1 when the magnitude is between 10 and 16. This is a 5-variable function over (a, b, c, d, e); magnitude 15 is a don’t-care because it isn’t reachable with 4-bit signed inputs (max positive sum = +14). Minterms are {10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22} with don’t-care {15}, and the minimum SOP factors cleanly along the sign:

T = ab’(c’ + d’ + e’) + a’b(c + d)

That factoring reflects what’s happening physically: the function looks completely different on the positive side (a=0) than the negative side (a=1), and a 2-to-1 split at the sign bit is the natural seam.

Ones BCD — positive side

Positive-side functions over four magnitude variables (b, c, d, e), with don’t-cares baked into the unreachable inputs. After 32×8 minimization:

N0pos = bc’d’          (digit 8 or 9)
N1pos = b’c + cd        (digit 4 through 7)
N2pos = b’d + bcd’       (digit 2, 3, 6, 7)
N3    = e                (LSB direct wire)

All three positive-side ones bits realize on a 74153 with zero external gates — every MUX residual is a constant or a single variable.

Ones BCD — negative side

Negative-side functions read the raw adder bits, where the bit pattern encodes 16 minus the magnitude. Four-variable minimum SOPs:

N0neg = b’cde + bc’d’e’
N1neg = b’c’d’ + c’de’ + bc’e + bcd’e’
N2neg = b’d’e’ + bd’e + bde’ + b’c’de

The negative side is harder than the positive side because the don’t-care set is empty — every magnitude from 1 to 16 is reachable with at least one (X, Y) pair. Total negative-side gate count: 5 external gates, mostly 2-input ANDs feeding MUX data inputs.

Sign-merge routing

A 74157 quad 2-to-1 MUX with select = a routes the positive-side path (a = 0) or the negative-side path (a = 1) through to the 7447 BCD decoders. T, N0, N1, and N2 each get one channel of the 74157. N3 (= e) wires directly to the ones 7447 with no merge needed, since it’s the same signal regardless of sign.

Design Documentation

Numbering convention

The 5-bit adder output uses MSB-first indexing: R0 (a) is the sign bit, driving the sign LED and the 74157 select; R1 (b) is the magnitude MSB; R2 (c) and R3 (d) are middle magnitude bits; R4 (e) is the magnitude LSB. BCD outputs are labeled T (tens), N0 (ones 8-weight), N1 (ones 4-weight), N2 (ones 2-weight), and N3 (ones 1-weight = e, a direct wire).

Adder stage

The adder is built from two 74283 chips. Chip A sums bits 0–3 of the sign-extended inputs and produces magnitude bits R1–R4. Chip B contributes a single 1-bit adder stage that takes the replicated MSBs of X and Y as its A and B inputs and Chip A’s Cout as its Cin; its sum output is R0, bit 4 of the 5-bit signed result. The remaining three stages on Chip B are unused (A and B inputs tied to GND, sum and Cout outputs left disconnected).

Sign-extending each 4-bit input to 5 bits before adding is what keeps the result’s sign correct across the whole input range. Treating Chip A’s Cout as bit 4 directly (without the second stage) zero-extends the inputs and breaks signed addition for negatives — that was the bug caught at the breadboard with A = −8 and B = 0.

Chip B pin	Wired to
A1	X.MSB (replicated)
B1	Y.MSB (replicated)
C0 (Cin)	Chip A Cout
Σ1	R0 (sign bit / bit 4 of result)
A2–A4, B2–B4	GND
Σ2–Σ4, C4	unused (no connection)

MUX chip layouts — Chips 1–4 (74153 pairs)

Each 74153 contains two 4-to-1 MUXes sharing control pins CB (MSB) and CA (LSB). CB/CA are chip pin labels, distinct from signals A–E.

Chip 1 — 74153. CB = B (R1), CA = D (R3). Pure MUX, no external gates.

Input	1Y: N1pos	2Y: N2pos
I₀	C (R2)	0 (GND)
I₁	C (R2)	1 (VCC)
I₂	0 (GND)	C (R2)
I₃	C (R2)	0 (GND)

Chip 2 — 74153. CB = B (R1), CA = C (R2). 1 external OR gate.

Input	1Y: T|A=0	2Y: T|A=1
I₀	0 (GND)	1 (VCC)
I₁	0 (GND)	D’ + E’ (gate #1 OR)
I₂	D (R3)	0 (GND)
I₃	1 (VCC)	0 (GND)

Chip 3 — 74153. CB = B (R1), CA = D (R3). 3 external gates (2 AND + 1 XOR); C’ is one inverter fanning to I₀, I₃, and gates #4/#6.

Input	1Y: N1neg	2Y: N2neg
I₀	C’ (R2 inv)	E’ (R4 inv)
I₁	C’E’ (gate #4 AND)	C’E (gate #6 AND)
I₂	C⊕E (gate #5 XOR)	E (R4)
I₃	C’ (R2 inv)	E’ (R4 inv)

Chip 4 — 74153. CB = B (R1), CA = C (R2). 2 external AND gates.

Input	1Y: N0pos	2Y: N0neg
I₀	0 (GND)	0 (GND)
I₁	0 (GND)	DE (gate #2 AND)
I₂	D’ (R3 inv)	D’E’ (gate #3 AND)
I₃	0 (GND)	0 (GND)

74157 routing MUX — Chip 5

Select = A (R0, sign bit). A = 0 passes the positive side; A = 1 passes the negative side.

Channel	A input (pos)	B input (neg)	Output
1	Chip 2 1Y (T|A=0)	Chip 2 2Y (T|A=1)	T → tens 7447
2	Chip 4 1Y (N0pos)	Chip 4 2Y (N0neg)	N0 → ones 7447
3	Chip 1 1Y (N1pos)	Chip 3 1Y (N1neg)	N1 → ones 7447
4	Chip 1 2Y (N2pos)	Chip 3 2Y (N2neg)	N2 → ones 7447

N3 (ones 1-weight) = E (R4) as a direct wire to the ones 7447 pin A.

External gates — 6 total

#	Gate	Expression	Feeds	Source
1	OR	D’ + E’	Chip 2, 2Y I₁	R3, R4
2	AND	DE	Chip 4, 2Y I₁	R3, R4
3	AND	D’E’	Chip 4, 2Y I₂	R3, R4
4	AND	C’E’	Chip 3, 1Y I₁	R2, R4
5	XOR	C⊕E	Chip 3, 1Y I₂	R2, R4
6	AND	C’E	Chip 3, 2Y I₁	R2, R4

7447 BCD wiring

7447	Pin A (1)	Pin B (2)	Pin C (4)	Pin D (8)
Tens	T (from 74157 Ch1)	GND	GND	GND
Ones	N3 = E direct	N2 (74157 Ch4)	N1 (74157 Ch3)	N0 (74157 Ch2)

Sign LED: A (R0) direct — active high = negative.

Chip list

Chip	Qty	Role
74283	2	4-bit full adders — Chip A sums bits 0–3, Chip B contributes one stage for bit-4 sign extension
74153	4	Dual 4-to-1 MUX — BCD function generation
74157	1	Quad 2-to-1 MUX — sign-split merge
7447	2	BCD to 7-segment decoders (tens + ones)
7486	1	XOR gate (C⊕E)
7432	1	OR gate (D’ + E’)
7408	1	AND gates (DE, D’E’, C’E’, C’E)
7404	1	Inverters (C’, D’, E’)

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Working rules: propose, don’t execute

Three-tier classification for my design notes:

1. Direct consequences of confirmed decisions. Truth tables, expressions, anything that follows mechanically from encoding and rules. Written freely.
2. Mechanism that implements confirmed behavior unambiguously. Wire plans for stated rules, shared subexpressions that follow from per-side requirements. Written, but flagged as mechanism when I haven’t seen the implementation.
3. Choices that picked between plausible alternatives. Encoding, topology, architectural seams, component selection. These do not appear in Key Design Decisions as fait accompli. Either discussed and verified with me before being written up, or flagged in an Unconfirmed subsection naming the alternative that was not picked.

Anti-patterns I watch for: fabricating specifics past what we discussed; picking between real alternatives without showing me; after-the-fact justification framing (“we picked X because…”) with no trace that Y and Z were considered; restructuring passes silently promoting proposals to decisions.

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Circuit 4: register-based max finder (CircuitVerse simulation)

Four 4-bit registers store values as they arrive; a fifth register holds the running maximum across them. An ADD button commits the current DIP-switch input into the next available storage slot and, independently, updates the max register if the new value exceeds what’s already there. A CLEAR button resets every slot and the max. A FULL LED lights once all four storage slots are occupied and freezes further updates until CLEAR.

Open the CircuitVerse simulation →

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Inputs, outputs, and behavior

Inputs

• INPUT[3:0] — 4-bit unsigned value on DIP switches, range 0–15.
• ADD — pushbutton. Rising edge advances the fill counter, conditionally updates R_MAX, and (if not full) commits INPUT to the register pointed to by the counter.
• CLEAR — pushbutton. Asynchronous reset — clears all storage registers, R_MAX, the fill counter, and the FULL latch to zero.

Outputs

• R_MAX.Q[3:0] — 4 output probes, binary readout of the current maximum.
• FULL — 1 red LED. Lights HIGH when all four storage registers are occupied; cleared by CLEAR.

Behavior

• CLEAR pressed: All five PIPO registers, the fill counter, and the FULL latch asynchronously reset to 0.
• ADD pressed, FULL = 0: INPUT loads into the register pointed to by the fill counter (R0 if 00, R1 if 01, R2 if 10, R3 if 11). The counter advances, saturating at 11. Independently, if INPUT > R_MAX then R_MAX takes the new value; otherwise R_MAX holds.
• ADD pressed, FULL = 1: All LOAD lines are gated to 0 by NOT-FULL — no storage register loads. The counter stays at 11. R_MAX.EN is also gated by NOT-FULL, so R_MAX freezes even if a post-full INPUT exceeds the stored max. FULL stays HIGH until CLEAR.

Boolean expressions and truth tables

The register bank, the fill counter, the LOAD decoder, the FULL latch, and the R_MAX enable all come from a small set of expressions. Walking the data path from the register primitive outward:

PIPO register subcircuit

Each 4-bit register is a subcircuit built from four of CircuitVerse’s featured D flip-flops sharing the same CLK, EN, and asynchronous RES signals. D[3:0] enters through a splitter and fans out one line to each DFF’s D pin; Q[3:0] joins back out through a splitter on the opposite side. The featured DFF’s built-in EN pin carries the load-enable directly — no external 4-bit 2-to-1 mux was needed to choose between “load” and “hold.”

Fill counter — 2-bit saturating up-counter

Q0Q1 is both the count of filled registers and the pointer to the next register to fill. Next-state table:

| Q0 Q1 | Q0' Q1' |
|-------|---------|
|  0  0 |   0  1  |
|  0  1 |   1  0  |
|  1  0 |   1  1  |
|  1  1 |   1  1  |  (saturates)

Deriving the D inputs from the table and simplifying by absorption (A + A’B = A + B):

D0 = Q0'Q1 + Q0Q1' + Q0Q1
   = Q0'Q1 + Q0
   = Q0 + Q1

D1 = Q0'Q1' + Q0Q1' + Q0Q1
   = Q1' + Q0Q1
   = Q1' + Q0

2-to-4 LOAD decoder

The decoder turns the counter’s pointer into a single active LOAD line, gated by NOT FULL so that a post-full ADD can’t overwrite a stored value:

LOAD_R0 = NOT FULL · Q0' · Q1'
LOAD_R1 = NOT FULL · Q0' · Q1
LOAD_R2 = NOT FULL · Q0  · Q1'
LOAD_R3 = NOT FULL · Q0  · Q1

FULL latch

A separate D flip-flop clocked by ADD tracks whether the bank is full. Its D input is a single AND:

D_FULL = Q0 · Q1

On the ADD edge where Q0Q1 is already 11 (the edge that fills R3), D_FULL is 1, so FULL latches HIGH on that same edge. It stays HIGH until CLEAR.

The counter is doing two jobs at once, and that’s why the FULL flip-flop is a separate piece of state. It tracks which register is next to fill (Q0Q1 as a 2-bit pointer: 00→R0, 01→R1, 10→R2, 11→R3), and it has to tell the rest of the circuit whether any registers are still empty — because once they’re all full, new inputs have to bounce off. A combinational Q0·Q1 tap tries to do both off the same two bits, but it conflates “pointing at the last slot” with “all slots full” — it would assert FULL while R3 is being loaded, not after. The two questions need two pieces of state. My saturating counter can’t tick past 11 to signal “done” on its own, so the FULL flip-flop is the second piece: D_FULL = Q0·Q1 latches HIGH on the clock edge after the pointer lands on R3, so FULL reads “done loading” rather than “pointing at the last slot.”

After I submitted, feedback on the design pushed me further, and an alternative surfaced that I hadn’t seen during scoping. It handles the same two jobs with different hardware — keep the counter as the pointer, but derive “any registers still empty” combinationally from R_MAX instead of latching it in a flip-flop. Let the counter wrap (00 → 01 → 10 → 11 → 00) instead of saturating, and put the “bank still has room” logic outside the counter as an enable — ENABLE = Q0 + Q1 + Reg_MT, where Reg_MT is “some register is still empty.” That enable gates both the counter’s advance and every register’s load. The catch is where Reg_MT comes from. Source it from R_MAX by checking whether all four bits are zero and I save the whole flip-flop — but I also commit to calling an all-zero input stream “empty.” On random 4-bit inputs that misclassification rate is (1/16)⁴ ≈ 0.0015%. As I put it when I worked through this: if you’re checking four zeros against each other to see what’s biggest, you have bigger problems than the 0000 empty state.

The flip-flop savings aren’t free, though. Counting gates: the R_MAX zero-detect is a 4-input NOR, the enable needs a 3-input OR to fold in Q0 and Q1, and the counter needs ANDs on its D-paths so ENABLE = 0 freezes the advance. The FULL latch I shipped costs one AND (D_FULL = Q0·Q1) and one inverter for NOT FULL. So the alternative saves a flip-flop but spends a bunch of gates on the outside logic. I didn’t see this alternative until feedback pushed me to look for it — but even after working through it, I still think counter+FULL is the more elegant path.

R_MAX enable

R_MAX shares the INPUT bus with the four storage registers; its EN pin alone decides whether the current INPUT becomes the new max. One AND gate handles both the “new value is actually bigger” condition and the “bank is full, freeze everything” condition:

R_MAX.EN = NOT FULL · CMP_MAX.GT

| FULL | GT | EN | R_MAX behavior      |
|------|----|----|---------------------|
|   0  |  0 |  0 | hold (INPUT ≤ max) |
|   0  |  1 |  1 | load new max        |
|   1  |  0 |  0 | frozen (bank full)  |
|   1  |  1 |  0 | frozen (bank full)  |

The NOT-FULL half of this gate was added after the verification sweep caught R_MAX drifting past FULL on a post-full input spike.

Stretch (contingent on feedback)

• Display-on-demand. A LOAD button and a separate R_DISP register, so the current max reads out only when requested rather than continuously.
• Decimal display. GE10 detect + subtract-10 path feeding two 7447 decoders, for a two-digit seven-segment readout.
• 4-bit adder subcircuit. Required by the decimal-decode path.

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Circuit 5: Rock-Paper-Scissors judge (CircuitVerse simulation)

Two-player rock-paper-scissors judge. Each player picks Rock, Paper, or Scissors on a one-hot three-switch input; a reveal button gates the display; two common-cathode RGB LEDs signal per-player outcomes — green for a win, blue for a tie, red for an invalid input on that side. Purely combinational — no latching, no clocks.

Open the CircuitVerse simulation →

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Inputs, outputs, and behavior

Inputs

• A_R, A_P, A_S — Player 1 move, one-hot. Exactly one high for a valid entry.
• B_R, B_P, B_S — Player 2 move, one-hot.
• button — momentary reveal enable. Held → blues and greens display; released → blues and greens go dark. Reds are not gated by the button.

Outputs

• P1_Red, P1_Green, P1_Blue — Player 1 side of a common-cathode RGB LED.
• P2_Red, P2_Green, P2_Blue — Player 2 side of a common-cathode RGB LED.

Per-side color semantics: green — this side wins the round; blue — tie (lights on both sides simultaneously); red — this side’s input is invalid.

Simulation representation. CircuitVerse’s RGB LED component expects 8-bit inputs per channel (intensity 0–255), which doesn’t match the 1-bit on/off signals from this circuit. The schematic uses three discrete LEDs per side (red, green, blue, tinted via the component color property), wired to the three per-side signals. This arrangement represents a common-cathode RGB LED as it would appear in a real build — the shared ground across the three channels corresponds to the common cathode pin.

Behavior

• Both sides valid, winner exists: the winning side’s green lights while the button is held; the other side is dark; no reds.
• Both sides valid, tie: both blues light while the button is held; no greens, no reds.
• One side invalid: that side’s red lights immediately (button state doesn’t matter); the other side is dark; no greens, no blues.
• Both sides invalid: both reds light; no greens, no blues.
• Button released: blues and greens dark. Reds unaffected.

Boolean expressions and truth tables

The circuit decomposes into four stages: the per-player validating encoder, the tie detector (the comparator’s EQ output), the winner cluster (minimized with don’t-cares), and the priority chain at the LED stage. Each stage’s expressions below.

3-to-2 validating encoder (per player)

Inputs: A_R, A_P, A_S (one-hot). Outputs: the 2-bit code AL0, AL1 (MSB first) and an error flag E_A. Encoding:

| Move   | AL0 AL1 | count of 1s |
|--------|---------|-------------|
|   R    |  0   0  |      0      |
|   P    |  0   1  |      1      |
|   S    |  1   1  |      2      |
|  (gap) |  1   0  |      —      |

By inspection:

AL0 = A_S                                (only S has MSB = 1)
AL1 = A_P + A_S                          (both P and S have LSB = 1)
E_A = NOT(exactly one of {A_R, A_P, A_S} is high)

Same structure for player B, producing BL0, BL1, E_B from B_R, B_P, B_S.

Rule table — nine valid rows

Rock crushes scissors. Paper covers rock. Scissors cut paper.

| P1 | P2 | A-code (AL0 AL1) | B-code (BL0 BL1) | Awin | Bwin | Tie |
|----|----|------------------|------------------|------|------|-----|
| R  | R  |      0   0       |      0   0       |   0  |   0  |  1  |
| R  | P  |      0   0       |      0   1       |   0  |   1  |  0  |
| R  | S  |      0   0       |      1   1       |   1  |   0  |  0  |
| P  | R  |      0   1       |      0   0       |   1  |   0  |  0  |
| P  | P  |      0   1       |      0   1       |   0  |   0  |  1  |
| P  | S  |      0   1       |      1   1       |   0  |   1  |  0  |
| S  | R  |      1   1       |      0   0       |   0  |   1  |  0  |
| S  | P  |      1   1       |      0   1       |   1  |   0  |  0  |
| S  | S  |      1   1       |      1   1       |   0  |   0  |  1  |

All 55 other input combinations set E_A = 1 or E_B = 1 (or both), and the priority chain at the LED stage suppresses the winner and tie outputs whenever either side is invalid.

Tie detection

Tie = EQ                     from a 4-bit magnitude comparator with
                             A = { 0, 0, AL0, AL1 }
                             B = { 0, 0, BL0, BL1 }

The upper two bits of each comparator operand are tied low (the codes are 2-bit), so EQ asserts exactly when the two codes match — the three tie rows in the rule table above.

Winner detection — 5-variable minimization with don’t-cares

Variables for the minimization: X (the comparator’s A>B output) and the four code bits AL0, AL1, BL0, BL1. Winner minterms enumerated from the rule table as 5-bit vectors X‑AL0‑AL1‑BL0‑BL1:

A winners:
  R beats S    X=0  A=00  B=11   →  00011  (3)
  P beats R    X=1  A=01  B=00   →  10100  (20)
  S beats P    X=1  A=11  B=01   →  11101  (29)

B winners:
  P beats R    X=0  A=00  B=01   →  00001  (1)
  S beats P    X=0  A=01  B=11   →  00111  (7)
  R beats S    X=1  A=11  B=00   →  11100  (28)

All nine tie rows plus all 55 rows with one or both sides invalid are marked as don’t-cares in the minimizer — the priority chain at the LED stage handles those cases. 32×8.com returns:

Awin = AL1'·BL0  +  AL0'·BL1'  +  AL1·BL1
     = AL1'·BL0  +  (AL0 XNOR BL1)

The AL0'·BL1' + AL1·BL1 pair factors to (AL0 XNOR BL1) after pulling out the common structure — verified by expanding the XNOR against the original three Awin minterms. Observation: the X variable drops out entirely. The comparator’s A>B output is available to the minimizer but doesn’t appear in the final expression — the don’t-cares subsume the need for it.

Bwin via a single inverter

Under the “both valid, not tied” restriction, the 3 Awin minterms and the 3 Bwin minterms partition the space — so Bwin = NOT Awin by definition over that restriction, before any minimization is run. Running De Morgan on the minimized Awin confirms it algebraically:

Awin      = AL1'·BL0  +  (AL0 XNOR BL1)
NOT Awin  = (AL1 + BL0')·(AL0 XOR BL1)        [De Morgan + XNOR negation]
          = Bwin

To decide which of the two to actually build, I minimized Bwin independently as SOP on 32×8.com. Unlike Awin, Bwin’s minimized SOP kept the A<B (comparator complement) term — the don’t-cares didn’t absorb it — and it didn’t factor into a clean XNOR the way Awin did. The gate count came in about one gate higher than Awin, with several more inverters. So the build uses the minimized Awin and hangs a single inverter on the output to produce Bwin — fewer gates than a parallel winner network, and the two outputs can’t drift out of sync during edits.

Priority chain at the LED stage

V        = NOR(E_A, E_B)             (both sides valid)
enable   = V · button                (single AND at the enable node)

P1_Red   = E_A                       (not button-gated)
P2_Red   = E_B                       (not button-gated)
P1_Blue  = EQ · enable               (both sides blue on a tie)
P2_Blue  = EQ · enable
P1_Green = Awin · EQ' · enable
P2_Green = Bwin · EQ' · enable

The EQ' term on the greens suppresses green-on-tie leakage; the enable term suppresses all blue and green output when the button is released or either side is invalid. Reds pass through directly from the encoder error flags, so a player sees their own invalid-input indication while still picking their move.

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Architectural seam: the enable input

Everything upstream of the final enable AND — encoders, comparator, winner logic, and the LED priority chain — is combinational and doesn’t depend on how the enable signal is produced. That makes the reveal mechanism a swappable front end. Shape A (the build) uses enable = V · button. Shape B, documented as a stretch extension, swaps the button for a sequential one-shot that turns a press into a self-clearing pulse — the judge core is unchanged.

Stretch (future extension)

• Shape B — timed reveal wrapper. A sequential one-shot driven by the button edge; its output reveal_active replaces button in enable = V · reveal_active. Tap once, see the outcome for a fixed window, auto-clears — instead of “hold to see the result.”
• ROM-based rule lookup. The encoder output bus (two 2-bit codes plus two error flags) is a clean address-worth interface; a future CP3 ROM could replace the comparator and winner cluster with a lookup table without touching the input stage.

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Circuit 1: signed 3-bit multiplier with signed, base 10, seven segment output

This circuit takes two 3-bit inputs A₁A₂A₃ and B₁B₂B₃ that are both 2’s complement values and multiplies them together. The output is formatted as a sign and magnitude value and displayed on three 7-segment displays. There is no overflow detection in this circuit, as all possible output values between negative 12 and positive 16 are capable of being displayed.

Click for the CircuitVerse Demo

Documentation

• Design Narrative
• 3-bit Multiplier Overview
• Hand written work sample
• LED decoding truth table
• Boolean expressions for lighting LED segments
• Selected K-Maps

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Circuit 2: finds the largest of three 4-bit binary numbers and displays the largest value.

This circuit takes three 4-bit binary inputs X, Y and Z, and compares them, determining the largest. The largest value is displayed on two 7-segment displays. Three RGB LEDs (for X, Y and Z) show which of the numbers is largest with a green light. A red light indicates the number is the smallest of the three. Blue means the machine can’t determine the numbers relative magnitude.

Documentation

• Circuit Diagram
• Design Narrative
• Circuit 2 Truth tables
  • L >= 10
  • Base 10 Conversion for SevSeg LED
  • Largest/Smallest/Unknown Indicator LEDs